1. Field of the Invention
The present invention relates to a power supply wiring structure and a designing method of a power supply wiring.
2. Description of the Related Art
A semiconductor integrated circuit comprises a greater number of minute wirings such as clock wirings, signal wirings, power supply wirings, etc. compared to an ordinary conductive wiring. When an electric current is flown into such minute wirings, migration of electrons occurs. The migrated electrons urge atoms (for example, copper atoms, aluminum atoms, etc), which forms the wiring, thus causing an atomic depletion (void). Such void induces a decrease of a cross sectional area of a wiring film, an increase of the electric current density, and a temperature increase caused by Joule heat. More accelerated growth of the void finally comes to break down the wirings. Such phenomenon is referred to as electro migration (referred to as EM hereinafter).
In the recent semiconductor integrated circuit technology, gate length of transistors constituting a semiconductor integrated circuit is shortened to improve the degree of integration. When the degree of the integration is improved in this manner, it is possible to reduce the area of the semiconductor integrated circuit. However, the number of operating transistors per unit area is increased thus increasing the consumed electric current per unit area. As a result, the electric current density in the power supply wiring is increased and a problem of EM in the power supply wiring becomes significant.
In the meantime, the wiring of the semiconductor integrated circuit is formed by electrically connecting multilayer wirings through vias. With the same amount of electric current, the EM problem is more significant in the vias than in the wirings. This is due to a meteoric failure phenomenon. The meteoric failure phenomenon will be described in the followings.
In the recent manufacturing procedure of a semiconductor integrated circuit, a great number of vias are concentrated so that there is a swollen part by the vias in an area with a great number of the concentrated vias compared to an area where the vias are not concentrated. The density of via numbers per unit wiring is referred to as a via density. Due to such swollen part by the vias, the wiring becomes let out and connected to other wirings at the time of forming a wiring which is a layer over the via. Such phenomenon is referred to as the meteoric failure phenomenon.
The wiring width of the power supply wiring is wider than that of the signal wiring, so that it is possible to form a grater number of vias compared to the case of the signal wiring. Thus, in order to avoid the meteoric failure phenomenon, the power supply wiring is designed with the decreased via density. However, with this, the cross sectional area of the via is decreased due to a decrease in the via density. Thus, the EM problem is more increased.
For the EM problem as described above, in the semiconductor integrated circuit, a standard of the allowable electric current density is set and the wirings and vias therein are so constituted that the electric current density falls within the allowable electric current density.
However, the recent semiconductor integrated circuit uses a multilayer structure. Further, the semiconductor integrated circuit is formed by disposing various cells or blocks as will be described below. Specifically, the semiconductor integrated circuit is constituted by disposing various cells or blocks, e.g. logic cells such as an AND circuit and OR circuit with relatively small power consumption, sequence cells such as an FF circuit and a latch circuit, a memory cell such as SRAM with relatively a large power consumption, etc.
Because of the structural reasons, there is a locally-declined power consumption of the circuit generated in the semiconductor integrated circuit, resulting in complication of the electric current paths from the power source to the transistor. Thus, it becomes difficult to calculate the allowable electric current density of the wiring and the via. In addition, it is difficult to specify the section within the semiconductor integrated circuit where the EM becomes an issue.
Furthermore, when looking into the blocks of the semiconductor integrated circuit, there raise the following shortcomings. That is, even if the EM problem is eliminated in each block, there may have an EM problem when the power supply wiring within the block is a bypass circuit of the power supply wiring for the other high-power-consumption block though there is no EM problem generated in that block, due to the corresponding relation between the bypass circuit and the semiconductor integrated circuit as a whole.
Because of the reason described above, when designing the blocks within the semiconductor integrated circuit, it is necessary to design the circuit for excessively supplying power so as not to have the EM problem. Furthermore, when designing each block of the semiconductor integrated circuit, used is a designing method in which a power supply wiring area necessary for the block is determined based on the consumed electric current of each block, and the EM problem is not generated if the area of the power supply wiring occupying the block is a prescribed value or more. When the block design is carried out by such block designing method, there is an excessive power supply area provided in the designed block. As a result, the power supply area of the semiconductor integrated circuit is increased thus hindering the size-reduction of the semiconductor integrated circuit.
Japanese Patent Unexamined Publication (JP-A 5-226331) discloses the related art which is directed to coping with the EM problem of the vias in the power supply wiring as described above. In the followings, the power supply wiring structure of the related art will be described.
FIG. 13A and FIG. 13B illustrate an example of an electric power supply wiring structure of the related art. In FIG. 13A, reference numeral 12010 is a first power supply wiring before modification. 12020 is an original width of the first power supply wiring 12010. 12030 is a width of the power supply wiring 12010 after the modification. 12040 is a wiring extending direction of the first power supply wiring 12010. 12050 is a second power supply wiring. 12060 is a width of the second power supply wiring 12050. 12070 is a wiring extending direction of the second power supply wiring 12050. 12080 is a first power supply wiring area. 12090 is a via. 12100 is a notable power supply wiring part. The first power supply wiring 12010 illustrated in the drawings by a broken line is connected to the second power supply wiring 12050 through the via 12090. The via 12090 is disposed in an area where the first power supply wiring 12010 and the second power supply wiring 12050 cross each other. The width 12030 of the first power supply wiring 12010 after the modification is formed wider than the width 12060 of the second power supply wiring 12050.
The effect achieved by the structure of the semiconductor integrated circuit as described above will be described in the followings. In the semiconductor integrated circuit formed in multiple layers, in the manufacturing procedure thereof, a great number of different masks are stacked many times to be disposed at the same position for forming the wirings and the vias. Thus, when stacking the masks at the same position, shift in the masks cause problems, e.g. a short circuit of the wiring between the upper layer wiring and the lower layer wiring, floating of the via, etc.
In the related art for overcoming such problems, the first power supply wiring is formed with the modified width 12030 of the first power supply wiring 12010, which is wider than the width 12020 of the first power supply wiring 12010 before the modification. With this, it is possible to prevent a decrease in the yield of the semiconductor integrated circuit even if there is a shift in the position of the via in the manufacturing procedure of the semiconductor integrated circuit.
Next, FIG. 13 B is a cross sectional view of the notable power supply wiring part 12100 shown in FIG. 13A. Reference numeral 12110 is a first power supply wiring 12110. 12120 is a height of the first power supply wiring 12110. 12130 is a second power supply wiring. 12140 is a height of the second power supply wiring 12130. 12150 is a via. 12160 is a width of the first power supply wiring 12110 before modification. 12170 is a width of the first power supply wiring 12110 after modification. 12180 is a flow direction of the electric current. 12190 is a width of the second power supply wiring 12130.
For the wirings of the semiconductor integrated circuit, the heights of the wirings are formed to be uniform since it is easier for manufacture. Thus, the height 12120 of the first power supply wiring 12110 and the height 12140 of the second power supply wiring are set to be an arbitrary height without any specific reasons. Further, since the heights of the wirings are uniform, in a regular state, if the width of the power supply wiring is determined, the resistance of the power supply wiring and the electric current density of the power supply wiring are determined uniquely.
The direction 12180 of the electric current flows from the second power supply wiring 12130 towards the first power supply wiring 12110 through the via 12150. In the related art, the width 12160 of the first power supply wiring 12110 before the modification is widened to the proposed width 12170 of the first power supply wiring 12110. By widening the wiring width in this manner, the resistance of the first power supply wiring 12110 is reduced so that still larger amount of the electric current is to be flown.
However, there is no increase in the number of the via 12150. Thus, even if the resistance of the first power supply wiring 12110 is reduced, there is no change in the electric current flown to the first power supply wiring 12110 from the second power supply wiring 12140. As described above, in the conventional structure, there is no measure taken for the via 12150 which is a bottleneck in overcoming the EM problem.
As is clear from those described above, the conventional structure shown in FIG. 13A and FIG. 13B is aimed at increasing the productivity (increase the yield) of the semiconductor integrated circuit, while an increase in the number of vias for the wiring is only taken as a means for avoiding a shift of the vias in the manufacturing procedure.
Next, by referring to FIG. 14A-FIG. 14C, described is a conventional method in which the number of vias for the wiring is increased. In FIG. 14A, reference numeral 13010 is a relation between the regularity of the wiring and a general yield. 13020 is a relation between the regularity of the wiring and the yield when particularly paying attention to the yield related to the via density at the crossing area between the wirings. 13030 is a relation between the overall yield and the regularity of the wiring.
When forming the wires in the semiconductor integrated circuit, by enhancing the regularity of the wirings through taking a measure such as arranging rectangular wirings at equal intervals, etc, for example, manufacture of the semiconductor integrated circuit becomes easy thus improving the productivity (yield) of the semiconductor integrated circuit. Thus, when looking at the yield, an increase in the regularity of the wiring improves the yield as can be seen in the relation 13010 between the regularity of the wiring and the yield.
However, for the overall yield of the semiconductor integrated circuit, in addition to the yield related to the regularity of the wiring, there is also the yield 13020 related to the via density at the crossing area between the wirings. By increasing the via density in the crossing area between the wirings, while the regularity of the wiring becomes deteriorated, the EM problem can be improved. For that, the yield is improved.
Therefore, when looking at the overall yield of the semiconductor integrated circuit, the overall yield 13030 is determined as a result of the multiplier of both an increase/decrease property 13010 of the ordinary yield related to the regularity of the wiring and an increase/decrease property 13020 paying attention to the via density at the crossing area of the wirings.
Further, the number of vias in the wiring will be described by referring to FIG. 14B and FIG. 14C. As shown in FIG. 13 and the like, an increase in the number of the vias enables to prevent a shift of the masks. However, if the number of the vias in all the wirings is increased in the semiconductor integrated circuit, there cause increases in the capacity of the signal wirings and in the area of the wirings. Thus, it is necessary to go with the following relational expressions for the number of vias.
Referring to FIG. 14B, in an area where an increase in the area and the wiring capacity is not a problem, the relation can be expressed by a following relational expression:Number of vias=number which causes no problem in manufacturing procedure+α  (1)
Next, referring to FIG. 14C, in an area where an increase in the area and the wiring capacity is a problem, the relation can be expressed by a following relational expression:Number of vias<number which causes no problem in manufacturing procedure+α  (2)
Based on these, since there are larger areas of the above-mentioned expressions (1) in the related art, it enables to reduce the possibilities of causing shift of the vias in the semiconductor integrated circuit.
Furthermore, as semiconductor integrated circuit designing methods, there are many designing methods in which a desired semiconductor integrated circuit is formed by stacking wirings in a rectangular shape as the wiring shape since it is easier to manufacture.
In the semiconductor integrated circuit, EM in the wiring and the via is an issue. Particularly, EM is a problem in the power supply wiring, since power is supplied to each transistor of the semiconductor integrated circuit therethrough and also a larger amount of electric current is flown compared to that of the signal wiring. Furthermore, in the recent designing method of the semiconductor integrated circuit, the via density is decreased to cope with the meteoric failure phenomenon. In addition, due to the substrate structure, when the cross sectional area of the wiring and that of the via being orthogonal to the direction of the electric current are compared, the cross sectional area of the via being orthogonal to the direction of the electric current is smaller than that of the wiring. Therefore, the EM problem is significant in the via. Further, in the multilayer structure which is used in the recent semiconductor integrated circuit, the electric current paths to the transistors become complicated so that it becomes difficult to cope with the EM by calculating the electric current density of the vias in each wiring layer and stage, which is locally concentrated.
In the power supply wiring structure shown in FIG. 13A and FIG. 13B, the wiring width of the power supply wiring where the EM is significant is widened so that the area of the power supply wiring is increased. Further, since designs of the power supply wiring and the signal wiring are modified for expanding the power supply wiring after detecting the section where the EM becomes an issue, there requires a great number of complicated steps for modifying the semiconductor integrated circuit. Moreover, in the semiconductor integrated circuit shown in FIG. 13B, the width 1219 of the second power supply wiring is simply widened to the still wider width 1217 of the power supply wiring, and there is no measure taken for the via where the EM problem becomes most significant.
Further, the number of vias in the power supply wiring structure of the related art corresponds to the shift of the vias caused in the manufacturing procedure of the semiconductor integrated circuit, which is designated in accordance with the expressions (1), (2) when determining the number of the vias in the wirings. Thus, it is not possible to cope with the EM problem of the vias when it occurs, thereby deteriorating the productivity (yield) of the semiconductor integrated circuit.